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= GSoCOldIdeas =
 
= GSoCOldIdeas =
 
=== Block header parsing tool ===
 
 
Rough ideas:
 
* Python-based tool
 
* Can extract info from block headers (and maybe, if it has to, also from the .cc file)
 
** Analyse factory signature ("make function"), analyze getters/setters
 
** Analyse I/O signature
 
 
Utilities:
 
* Auto-generate YAML files for GRC (would require another tool, also part of this project)
 
* Facilitate inclusion of GNU Radio with other tools/frameworks
 
 
There is some code in gr_modtool which does this, which can be reused and
 
extended.
 
 
===== Prerequisites =====
 
 
* Strong knowledge of Python, including Py3k idiosyncrasies
 
* Some text parsing experience
 
* Some understanding of GNU Radio block structure
 
 
===== Outcome =====
 
 
* A tool, written in Python, merged into the GNU Radio source tree, which can turn a block definition into some kind of abstract representation (the design which of is also part of this project)
 
* Another tool, which takes the abstract representation, and produces YAML files for GRC.
 
* An API into calling this which can be used by other tools (external to GNU Radio).
 
* Make gr_modtool use this tool instead of its builtin code.
 
 
===== Mentor(s) =====
 
 
Martin Braun, Nicolas Cuervo
 
 
 
 
=== Hardware in the Loop: Cycle-accurate Verilog Design Simulation Integration ===
 
 
Hardware accelerators are necessary or at least desirable in many SDR systems.
 
 
A typical development workflow for FPGA-accelerated DSP system looks like this:
 
 
* Write down the system specification, formulate the algorithm mathematically
 
* Implement the algorithm in Matlab, Python to make a Proof of Concept
 
* Write extensive test cases to make sure you've got everything right
 
* Iterate.
 
* Implement the same algorithm in a HDL, e.g. Verilog, and synthesize
 
* Write extensive (System)Verilog test benches, which mostly duplicate code from the software test cases in a less friendly development environment
 
* Run the test benches in simulation and the FPGA to prove functionality
 
* Iterate.
 
 
However, with [https://www.veripool.org/wiki/verilator Verilator], there's a relatively mature tool to turn Verilog modules into compilable C++ code that offers a cycle-accurate simulator of the module.
 
 
The goal would be to use integrate verilator into the GNU Radio in a way that allows for rapid prototyping of small, well-defined Verilog modules; the idea is that you can, in the end, just drop your Verilog code file name in a GNU Radio block, and behind the scenes, the C++ code is generated, necessary "adapters" from native (GNU Radio) data types to simulated signals are added, and all is then executed at flow graph run time to process digital signals from within a flow graph.
 
 
==== Prerequisites ====
 
 
* workable C++ proficiency
 
* basic idea of FPGA development
 
* Ability to read and write "hello world" verilog modules
 
 
==== Outcome ====
 
 
* Adapter code to call Verilator-generated Code of modules with fixed interface from within a GNU Radio block's work routine
 
* Integration of verilator into either build infrastructure or runtime infrastructure (might require further dependencies, e.g. llvm)
 
* Examples and software test cases for fundamental blocks, e.g. a FIFO and a integer squarer
 
 
==== Mentor ====
 
 
Marcus Müller
 
 
  
  
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Martin Braun, Nicolas Cuervo
 
Martin Braun, Nicolas Cuervo
 
  
 
=== DTV User Front-End ===
 
=== DTV User Front-End ===
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Sebastian Müller, Sebastian Koslowski
 
Sebastian Müller, Sebastian Koslowski
  
 
=== Others ===
 
 
==== Improve PyBOMBS ====
 
==== Improve PyBOMBS ====
  

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