Dynamic Channel Model
The dynamic channel model is a hier block consisting of the following effects:
- Dynamic Frequency Selective Fading Channel
- Dynamic Center Frequency Offset Model
- Dynamic Sample Rate Offset Model
- Additive White Gaussian Noise
The desired power delay profile and max doppler frequency may be provided to achieve the desired Ricean or Rayleigh fading scenario. For center frequency and sample rate offset models, a gaussian random walk process is conducted for each. The single sample step variance and maximum deviation for these two processes is specified and may be modified to simulate various desired stability effects. Lastly AWGN is added to simulate a typical receiver/thermal noise floor after propagation, and the variance may be modified here as desired.
This model allows the user to set up an AWGN noise cource, a random walk process to simulate carrier frequency drift, a random walk process to simulate sample rate offset drive, and a frequency selective fading channel response that is either Rayleigh or Ricean for a user specified power delay profile.
- samp_rate (R)
- Input sample rate in Hz
- cfo_std_dev (R)
- carrier frequency drift process standard deviation per sample in Hz
- cfo_max_dev (R)
- maximum carrier frequency offset in Hz
- sro_std_dev (R)
- sample rate drift process standard deviation per sample in Hz
- sro_max_dev (R)
- maximum sample rate offset in Hz
- noise_amp (R)
- Specifies the standard deviation of the AWGN process
- N (R)
- number of sinusoids used in frequency selective fading simulation
- doppler_freq (R)
- maximum doppler frequency used in fading simulation in Hz
- defines whether the fading model should include a line of site component. LOS->Rician, NLOS->Rayleigh
- (Only if Rician is chosen above) Rician K-factor, the ratio of specular to diffuse power in the model
- A random number generator seed for the noise source.
- A list of fractional sample delays making up the power delay profile
- A list of magnitudes corresponding to each delay time in the power delay profile
- The length of the filter to interpolate the power delay profile over. Delays in the PDP must lie between 0 and ntaps_mpath, fractional delays will be sinc-interpolated only to the width of this filter.
Insert description of flowgraph here, then show a screenshot of the flowgraph and the output if there is an interesting GUI. Currently we have no standard method of uploading the actual flowgraph to the wiki or git repo, unfortunately. The plan is to have an example flowgraph showing how the block might be used, for every block, and the flowgraphs will live in the git repo.
- C++ files
- Header files
- Public header files
- Block definition